This application claims priority under 35 U.S.C.xc2xa7xc2xa7119 and/or 365 to 9902150-3 filed in Sweden on Jun. 8, 1999; the entire content of which is hereby incorporated by referenced.
The present invention relates to a method and to an arrangement for preventing metastability in conjunction with the receipt of an asynchronous signal in a first clock domain that has a first clock frequency from a second clock domain that has a second clock frequency.
When an asynchronous digital signal is received in one clock domain from another clock domain, it is possible that metastability will occur in receiving circuits, meaning that the output value from receiving circuits cannot be relied upon.
In simpler terms, it can be said that metastability occurs when the switch between two states of the incoming signal takes place during the active edge of the clock that clocks the receiving flip-flop.
Reference is made to the publication xe2x80x9cContemporary Logic Designxe2x80x9d by Randy H. Katz at the University of California, published 1993 by Benjamin Cummings/Addison Wesley Publishing Company, with particular reference to the chapter bearing the title xe2x80x9cMetastability and Asynchronous Inputsxe2x80x9d, this chapter being accessible on the Internet via the following URL:
http://http.cs.berkeley.edu/xcx9crandy/CLD/chapter6/chapter06.doc4.html
The method most used to overcome problems with metastability is to receive the signal via two mutually sequential flip-flops, which causes metastability to die out between the flip-flops.
Another solution is to use a flip-flop and a clock frequency that is sufficiently low to allow the metastability to settle during a clock cycle or a clock period of the clock frequency used. The problems with metastability increase with higher transfer times.
At sufficiently high transfer speeds, a clock period is of such short duration as to prevent metastability from dying out during a clock period. In addition to not knowing whether the received signal is correct or not, it is also uncertain whether or not metastability is able to spread to following circuits and so on through a receiving system.
Several ways of solving the specific problems relating to transmission between two clock domains that have mutually different clock frequencies are known to the art.
Patent Publication U.S. Pat. No. 5,867,695 describes a method and a system adapted to provide communication between units that function with mutually different clock frequencies. Periods during which metastability can occur are determined by evaluating clock frequency differences. Data transmitted from one unit to the other is processed continuously.
Data is received via a special process during periods in which metastability can occur, while data is received directly in other periods. The special process comprises clocking-in data via two mutually sequential flip-flops.
Patent Publication U.S. Pat. No. 5,602,878 also describes how information is received via double flip-flops when there is a danger of metastability occurring, this information otherwise being received directly.
Patent Publication U.S. Pat. No. 4,525,849 describes the possibility of receiving information sent from one clock system to a receiving, independent asynchronous clock system with the aid of a buffer in coaction with different synchronisation circuits.
Patent Publication GB-A-2 262 415 describes a method and an apparatus with which a handshake process is used, thereby enabling two different systems operating in different clock domains to determine when information can be transmitted without risk of metastability occurring.
Patent Publications EP-A2-0 436 371 and U.S. Pat. No. 5,764,710 are further documents that deal with metastability problems.
It should also be mentioned that metastability is, in itself, energy consuming, due to the fact that metastable flip-flops switch between two states or modes, which requires energy.
The traditional solution of using two mutually sequential flip-flops is also energy consuming, because it utilises two flip-flops instead of one.
Technical Problems
When considering the present standpoint of techniques as described above, with a starting point from a method or an arrangement used in conjunction with receiving an asynchronous digital signal in a first clock domain that operates with a first clock frequency and which is derived from a second clock domain that operates with a second clock frequency, wherein said second clock frequency is known within the first clock domain, wherein a reference signal is available within the first clock domain, and wherein phase information from said reference signal is available in the second clock frequency, although with some uncertainty, it will be seen that a problem resides in finding a possibility of receiving said signal without risking the occurrence of metastability among receiving circuits in the first clock domain.
This is a particular problem from a technical aspect when the first clock frequency is so high that any metastability that may occur is unable to die out during a single clock period of the clock frequency in the first clock domain, which does not only result in an unreliable signal from a metastable circuit but also that the metastability can spread into other circuits in the first clock domain.
Another technical problem is one of defining a safe time period during which the received signal can be read without the risk of metastability.
A further technical problem resides in utilising the known relationship between the reference signal and the second clock frequency in order to find such a safe time period.
Yet another technical problem resides in realising how a reference signal or a clock frequency for the second clock domain can be generated on the basis of the aforesaid solution to generating said safe period.
When the first clock frequency is higher than the second clock frequency, a technical problem also resides in providing continuous access to the value of the received signal during a full period of the second clock frequency, even when the duration of the secure time period corresponds, e.g., to one period of the first clock frequency.
Solution
With the intention of solving one or more of the aforesaid technical problems, the present invention takes as its starting point a method, or an arrangement, for preventing metastability in conjunction with the receipt of an asynchronous digital signal in a first clock domain that operates with a first clock frequency, wherein said received signal is derived from a second clock domain that operates with a second clock frequency, wherein the second clock frequency is known within the first clock domain, wherein a reference signal having phase information that is known in the first clock domain is used as a clock frequency reference in the second clock domain, and wherein the phase information is found available in the received signal with a certain degree of uncertainty.
With the intention of enabling the value of the received signal to be read safely without risk of said signal causing metastability, it is proposed in accordance with the invention that the received phase information, having said uncertainty, is used to read the received signal in a stable fashion.
According to the present invention, a reference signal can be generated in the first clock domain. This reference signal may comprise a third clock frequency that is used when transferring information from the first clock domain to the second clock domain, wherewith the information is also transferred from the reference signal to the second clock domain. The uncertainty in the phase information in the received signal resides in the uncertainty in the phase relationship between the second clock frequency and the third clock frequency.
The first clock frequency is higher than the third clock frequency and each period of the third clock frequency shall, in accordance with the invention, be divided into a first and a second part. The first part is corresponded at least by the uncertainty and begins each period, while the second part comprises the remainder of each period. The received signal is read during a specific period of the first clock frequency that falls within the second part of each said period.
The known relationship between the second and the third clock frequencies, in other words the magnitude of the uncertainty in the phase difference, thus enables a safe time period to be obtained for reading the received signal, this time period being the second part of one period of the third clock frequency.
By generating a pulse during the specific period of the first clock frequency, it is possible to use this pulse to indicate when it is safe to read the received signal.
According to the invention, a counter is used to count through a number of states that corresponds to the number of periods that the first clock frequency has time to pass through during one period of the third clock frequency, and that the pulse shall be generated during a predetermined state of the counter.
According to one known technique, the clock frequency operative in the second clock domain may be obtained from the first clock domain by reduction of the first clock frequency. According to the invention, this can be achieved by using the reference signal, and therewith the third clock frequency, as a reference for the clock frequency in the second clock domain, and said reference signal can be generated with a starting point from the time that it takes for the counter to count through its states.
Alternatively, it is possible according to the present invention to make the value of a reading accessible to the first clock domain over a time period that corresponds to a full period of the first clock frequency, subsequent to having read the received signal.
Said value is made available by receiving said signal in a 2:1 multiplexer which forwards the received signal solely during said specific period, and which also forwards a feedback signal from itself at each other period.
According to the present invention, this feedback is made possible by receiving the signal forwarded from the multiplexer on a flip-flop, such as a D flip-flop, where the output signal of said flip-flop constitutes the received signal available to the first clock domain, and the signal fed back to the multiplexer. The flip-flop is clocked by the first clock frequency and the pulse generated by the counter forms the requisite multiplexer enable signal.
Advantages
The advantages afforded primarily by an inventive method and an inventive arrangement reside in enabling an asynchronous signal from one clock domain to be received in another clock domain without the risk of metastability in the receiving clock domain, even in those instances when the clock frequency in the receiving clock domain is so high as to prevent the use of traditional metastability processing methods.
An inventive solution also consumes much less power than traditional metastability solutions, by virtue of the fact that there is used in accordance with one preferred embodiment only one flip-flop, which is not subjected to metastability. According to another preferred embodiment there is used an AND-gate instead of a flip-flop, which further reduces the power required, this preferred embodiment being described in more detail hereinafter with reference to preferred embodiments. The present invention also provides means for generating the third clock frequency, which can also be used as a reference frequency for the second clock domain.
The primary characteristic features of an inventive method are set forth in the characterising clause of the accompanying claim 1, while the primary characteristic features of an inventive arrangement are set forth in the characterising clause of the accompanying claim 12.